1. Field of Invention
The present invention relates to an electro-optical device such as a liquid crystal display device or the like, a driving method for the electro-optical device, an image processing circuit therefore, and electronic equipment using the electro-optical device as a display unit.
2. Description of Related Art
A related electro-optical device, for example, an active matrix liquid crystal display device will be described with reference to FIG. 15 and FIG. 16.
As shown in FIG. 16, a liquid crystal display device consists mainly of a liquid crystal display panel 100, a timing circuit 200, and an image signal processing circuit 300. The timing circuit 200 outputs a timing signal to be employed in respective units. A phase development circuit 301 included in the image signal processing circuit 300 inputs an image signal VID of one channel, develops it into image signals exhibiting N phases (N=6 in FIG. 15) of the image signal VID, and outputs the image signals. The image signal is developed into image signals exhibiting N phases thereof is to extend an application time during which a sampling circuit, to be described later, applies an image signal to each thin-film transistor. Consequently, it is intended to ensure long sampling time and charging/discharging time for a data signal applied to a thin-film transistor (TFT) panel.
An amplification/reversal circuit 302 reverses the polarity of image signals according to a criterion described below, amplifies the signals, and feeds the signals as image signals VID1 to VID6 exhibiting different phases to the liquid crystal display panel 100. The polarity of image signals being reversed means that the voltage levels of the image signals are alternately reversed with the potentials at the half points of the peak pulse amplitudes thereof as reference potentials. Whether or not to reverse the polarity of the image signals is determined according to a criterion described below. Specifically, the criterion is whether an adopted data signal application form defines that the polarity of image signals should be reversed (1) for each scanning line, (2) for each data signal line, or (3) for each pixel location. A cycle of reversal is set to one horizontal scanning period or a dot cycle. This related art will, for convenience, be described on the assumption that the criterion is whether an adopted data signal application form defines that the polarity of image signals should be reversed (1) for each scanning line.
Moreover, a pre-charging signal NRS produced by the timing circuit 200 is a reverse signal, that is, a polarity-reversed signal, and fed to the liquid crystal display panel 100.
Next, the liquid crystal display panel 100 will be described below. The liquid crystal display panel 100 has an element substrate and an opposite substrate opposed to each other while being spaced from each other. The space is filled with a liquid crystal. The element substrate and opposite substrate are formed with quartz substrates or made of a hard glass or the like.
On the element substrate, a plurality of scanning lines 112 is laid down parallel to an X direction in FIG. 16, and a plurality of data lines 114 are arranged in a Y direction orthogonal to the X direction. The data lines 114 are grouped in groups of six into blocks B1 to Bm. Hereinafter, the data lines are generically referred to as the data lines 114 or discretely referred to as the data lines 114a to 114f. 
At the intersections between the scanning lines 112 and data lines 114, gates of thin film transistors (TFTs) 116 serving as switching elements are connected on the scanning lines 112, sources thereof are connected on the data lines 114, and drains thereof are connected to pixel electrodes 118. Each pixel location is composed of the pixel electrode 118, a common electrode formed on the opposite substrate, and the liquid crystal clamped between the electrodes. The pixel locations are arranged in the form of a matrix at the intersections between the scanning lines 112 and data lines 114. A holding capacitor (not shown) is connected to each pixel electrode 118.
A scanning line drive circuit 120 formed on the element substrate places a pulsating scanning line signal sequentially on the scanning lines 112 according to a clock signal CLY output from the timing circuit 200, a reverse clock signal CLYINV, and a transfer start pulse DY. Specifically, the scanning line drive circuit 120 shifts the transfer start pulse DY fed initially during a vertical scanning period from one stage therein to another in synchronous with the clock signal CLY or reverse clock signal CLYINV, and thus outputs the scanning line signal sequentially to the scanning lines 112. Consequently, the scanning lines 112 are selected sequentially.
A sampling circuit 130 has sampling switches 131 connected to ends of the data lines 114, and thus has the sampling switches 131 associated with the data lines 114. The switches 131 are realized with n-channel TFTs formed on the element substrate. Image signals VID1 to VID6 are applied to the sources of the switches 131. Six switches 131 connected on data lines 114a to 114f belonging to a block B1 have the gates thereof connected on a signal line on which a sampling signal S1 is placed. Six switches 131 connected on data lines 114a to 114f belonging to a block B2 have the gates thereof connected on a signal line on which a sampling signal S2 is placed. Likewise, six switches 131 connected on data lines 114a to 114f belonging to a block Bm have the gates thereof connected on a signal line on which a sampling signal Sm is placed. The sampling signals S1 to Sm are signals used to sample the image signals VID1 to VID6 for each block during a horizontally effective display period.
Moreover, a shift register circuit 140 formed on the element substrate outputs the sampling signals S1 to Sm successively in synchronous with the clock signal CLX output from the timing circuit 200 or the reverse clock signal CLXINV according to the transfer start pulse DX. To be more specific, the shift register circuit 140 shifts the transfer start pulse DX fed initially during a horizontal scanning period from one stage therein to another in synchronous with the clock signal CLX or reverse clock signal CLXINV. The shift register circuit 140 narrows the pulse duration of each resultant pulsating signal so that the pulse duration will not be the same between adjoining signals. Consequently, the shift register circuit 140 outputs the sampling signals S1 to Sm successively.
In the foregoing configuration, when the sampling signal S1 is output, the image signals VID1 to VID6 are sampled and applied to the six data lines 114a to 114f belonging to the block B1. The image signals VID1 to VID6 are written in six pixel locations defined along a currently-selected scanning line by the TFTs 116 associated with the pixel locations.
Thereafter, when the sampling signal S2 is output, the image signals VID1 to VID6 are sampled and applied to the six data lines 114a to 114f belonging to the block B2. The image signals VID1 to VID6 are written in six pixel locations defined along the currently-selected scanning line by the TFTs 116 associated with the pixel locations.
Likewise, when the sampling signals S3, S4, . . . , Sm are output successively, the image signals VID1 to VID6 are sampled and applied to the six data lines 114a to 114f belonging to the block B3, B4 . . . , Bm respectively. The image signals VID1 to VID6 are written in six pixel locations defined along the currently-selected scanning line. Thereafter, the next scanning line is selected, and writing is repeated in the same manner as that mentioned above relative to the blocks B1 to Bm.
According to the foregoing driving method, the number of stages in the shift register circuit 140 for driving and controlling the switches 131 included in the sampling circuit 130 is one-sixth of the number of stages in a shift register required according to a driving method of driving the data lines point-sequentially. Moreover, the frequencies of the clock signal CLX and reverse clock signal CLXINV are also one-sixth of those of signals employed according to the point-sequential driving method. Thus, the number of stages in a shift register is decreased and power consumption. is reduced.
Each data line 114 is accompanied by a parasitic capacitor. The capacitor is formed because each data line 114 is opposed to an opposite electrode with the liquid crystal between them. After a data signal is applied to each data line 114, the TFT 116 is turned on in order to write the voltage on the data line 114 in the pixel location. A voltage is thus applied to the liquid crystal of each pixel location. However, since each data line 114 is accompanied by a parasitic capacitor, even when the data signal is applied to the data line 114, the potential on the data line 114 does not agree with the data signal immediately. The potential on the data line 114 varies depending on a time constant determined with the capacitance of the parasitic capacitor and a resistance exhibited by a line. When a predetermined time has elapsed since the start of application of the data signal, the potential on the data line 114 agrees with the data signal. In this example, the polarity of the data signal is reversed in units of a scanning line. The polarity of the potentials on the data lines 114 must therefore be reversed with the potential at the opposite electrode as a center for each horizontal scanning period. During a certain horizontal scanning period, the polarity of the potentials on the data lines 114 to which the data signal has not been applied are the reverse of the polarity of the data signal to be applied. This leads to a long time required until the potentials on the data lines 114 agree with the data signal.
In efforts to overcome the above drawback, a pre-charge circuit 160 is included. The pre-charge circuit 160 has switches 165 connected to the other ends of the data lines 114, and thus associated with the data lines 114. The switches 165 are realized with TFTs formed on the element substrate. The drains of the TFTs (or sources thereof) are connected on the data lines 114, and the sources (or drains) thereof are connected to a signal line on which a pre-charging signal NRS is placed. The gates of the switches 165 are connected on a signal line on which a pre-charge driving signal NRG is placed. The pre-charge driving signal NRG is a pulsating. signal that is driven high during a horizontal retrace line period from the instant selection of a certain scanning line is terminated to the instant a succeeding scanning line is selected and the image signals are applied to the data lines. The data lines 114 are pre-charged to the level of the pre-charging signal NRS through the switches 165. The potentials on the data lines 114 are then changed to the levels of the image signals VID1 to VID6 sampled through the switches 131. Consequently, the magnitudes of charge or discharge by which the data lines 114 are charged or discharged with the image signals VID1 to VID6 are so limited that the time required for writing is shortened.
However, when a method of driving a plurality of data lines simultaneously is adopted or when pre-charging is added as one step to the method of driving a plurality of data lines simultaneously, irregular luminance occurs in portions of a displayed image coincident with the borders among the blocks B1 to Bm. The irregular luminance occurs, especially, in a halftone regular pattern. The principles of the irregular luminance will be described in relation to the blocks B1 and B2 by taking for instance a case where a simple and uniform pattern is displayed. The image signal VID6 to be applied to the data line 114f belonging to the block B1 and adjoining the block B2 has, as shown in FIG. 17, the same voltage level as the image signal VID1 to be applied to the data line 114a belonging to the block B2 and adjoining the block B1. In general, the image signals VID1 to VID6 are set to voltage levels associated with a black level of a gray scale during a horizontal retrace line period.
FIG. 17 shows waveforms attained in a case where the polarity of the precharging signal NRS is the same as the polarity of the image signals VID1 to VID6 (FIG. 16 shows the signals VID1 and VID6 alone) applied to the data lines 114, and reversed in units of a scanning line. Hereinafter, an absolute value of a difference between a mean of the potentials on the data lines 114 to which the image signals VID have been applied and the potential on the data lines 114 to which the pre-charging signal NRS has been applied shall be referred to as a pre-charging voltage Vpre.
Referring to the waveforms shown in FIG. 17, the pre-charging voltage Vpre is set to a level associated with a black level of a gray scale in a normally-white mode (or a white level in a normally-black mode). This is because the data lines are temporarily pre-charged until the voltage on the data lines changes greatly.
Referring to FIG. 17, the pre-charge driving signal NRG is driven high at a timing t11 within a time interval within which the image signals applied are of positive polarity. All of the switches 165 are therefore turned on. All of the data lines 114 are pre-charged to the level of the pre-charging voltage Vpre through the switches 165. Thereafter, the pre-charge driving signal NRG is driven low. All of the data lines hold the pre-charging voltage Vpre because of their parasitic capacitors.
At a timing t12, the sampling signal S1 is driven high. The image signal VID6 is sampled and applied to the data line 114f belonging to the block B1 through the switch 131. The voltage on the data line 114f changes from the level of the pre-charging voltage Vpre of the pre-charging signal NRG, which has been held on the data line, to the voltage level of the image signal VID6. The voltage is then written in the pixel location defined along a currently-selected scanning line by the associated TFT 116. Thereafter, the sampling signal S1 is driven low.
At a timing t13, the sampling signal S2 is driven high. The image signal VID1 is sampled and applied to the data line 114a belonging to the block B2 through the switch 131. The voltage on the data line 114a belonging to the block B2 therefore changes from the level of the pre-charging voltage Vpre, which has been held on the data line, to the voltage level of the sampled image signal VID1. The voltage is then written in the pixel location defined along a currently-selected scanning line by the associated TFT 116.
In contrast, the data line 114f belonging to the block B1 and adjoining the block B2 is capacitively coupled to the data line 114a belonging to the block B2 with the liquid crystal layer between them. When the potential on the data line 114a of the block B2 changes from the level of the pre-charging voltage Vpre to the voltage level of the image signal VID1, the voltage on the data line 114f fluctuates while being affected by the voltage change, though writing the voltage on the data line 114f in the pixel location has already been completed.
An optical density in the pixel location defined along the data line 114f of the block B1 and a currently-selected scanning line is changed from a value proportional to a primary writing voltage (1) to a value proportional to a voltage (2) deviated by a voltage proportional to the fluctuation caused by the capacitive coupling. The same applies to timings t21, t22, and t23 within a time interval within which the data signals applied are of negative potential, to the other blocks B2 to Bmxe2x88x921 relative to the currently-selected scanning line, and to the other scanning lines selected.
However, the other data lines 114a to 114e belonging to each block are never (hardly) affected by a voltage change on the data line 114a belonging to an adjoining block. An optical density in a pixel location defined along each of these data lines and a currently-selected scanning line is retained at a value proportional to a primary writing voltage.
Thus, an optical density in a pixel location defined along the data line 114f belonging to a certain block is different from optical densities in pixel locations defined along the other data lines 114a to 114e. Therefore, even when an attempt is made to display an image with the pixel locations associated with pixels constituting the image held at the same optical density, irregular luminance occurs in portions of a displayed image coincident with the borders among the blocks B1 to Bm.
The irregular luminance can be overcome to some extent. Specifically, the pre-charging signal NRS is set to a voltage level whose absolute value varies depending on whether the pre-charging signal NRS is of positive or negative polarity. For example, when the pre-charging signal NRS assumes positive polarity, it is set to a voltage level whose absolute value is associated with a white level of a gray scale. When the pre-charging signal NRS assumes negative polarity, it is set to a voltage level whose absolute value is associated with a black level thereof. When an image signal of positive polarity is sampled, a voltage whose level is associated with the black level is written. When an image signal of negative polarity is sampled, a voltage whose level is associated with the white level is written. Consequently, the pre-charging signal NRS and writing voltage are canceled out. Therefore, the irregular luminance can be overcome to some extent. However, even when this method is adopted, it is impossible to overcome the irregular luminance to such an extent that the irregular luminance is indiscernible. Moreover, a direct voltage is applied to each pixel location during a short period from application of the pre-charging signal NRS to writing of primary data. This may cause deterioration of a liquid crystal.
The present invention attempts to at least break through the foregoing situation. An object of the present invention is to at least provide a driving method for an electro-optical device capable of making irregular luminance, which occurs in portions of a displayed image coincident with borders among blocks, indiscernible, and displaying the image with high quality, an image processing circuit, an electro-optical device, and electronic equipment.
According to an exemplary embodiment of the present invention, there is provided a driving method for an electro-optical device that has a plurality of scanning lines, a plurality of data lines, transistors located at the intersections between the scanning lines and data lines, and pixel electrodes connected to the transistors. Herein, the scanning lines are selected sequentially. During a period during which each scanning line is selected, image signals are applied simultaneously-to data lines belonging to each of blocks into which the data lines are grouped. This application is carried out sequentially for each block. The image signal to be applied to a first data line belonging to a selected block and adjoining a succeeding block is corrected in advance based on a predicted change in the potential on a second data line belonging to the succeeding block and adjoining the first data line. The corrected image signal is applied to the first data line.
In general, the plurality of data lines is capacitively coupled to one another with pixel locations among them. As far as the data lines belonging to the same block are concerned, sampling is carried out at the same timing. A change in the voltage on a certain data line will not affect the voltages on the other data lines. However, when it comes to data lines belonging to different blocks, a change in the voltage on one of the data lines will affect the voltage on the other data line. Specifically, the voltage on a data line located on one edge of a block fluctuates from its primary writing voltage when the voltage on a data line located on the other edge of an adjoining block changes to the voltage level of a sampled image signal. This causes irregular luminance to occur in portions of a displayed image coincident with borders among blocks.
In the driving method according to another exemplary embodiment of the present invention, a change in the voltage on the second data line belonging to a succeeding block is predicted. The image signal to be applied to the first data line is corrected in advance based on the predicted voltage change, and then applied to the first data line. Even if noise stemming from the voltage change on the second data line enters the first data line because of a coupling capacitor, the noise is canceled by the corrected image signal. Consequently, irregular luminance occurring in portions of a displayed image coincident with the borders among the blocks can be minimized successfully.
Incidentally, the voltage change on the second data line depends on the level of an applied image signal. Therefore, the voltage change on the second data line is preferably predicted based on the image signal. to be applied to the second data line.
In the driving method according to another exemplary embodiment of the present invention, preferably, an electro-optical device has sampling transistors for sequentially sampling image signals and applying the image signals to the data lines. The voltage change on the second data line is preferably predicted based on the image signal to be applied to the second data line and a voltage drop occurring at an associated sampling transistor. When the sampling transistors are realized with TFTs or any other field-effect transistors, the voltage drop varies depending on a source voltage of each sampling transistor. According to the various exemplary embodiments of the present invention, the voltage change on the second data line may be predicted in consideration of the voltage drop. Irregular luminance occurring in portions of a displayed image coincident with the borders among the blocks can be minimized more successfully.
According to another exemplary embodiment of the present invention, a driving method for an electro-optical device is to be adapted to an electro-optical device that has a plurality of scanning lines, a plurality of data lines, and transistors and pixel electrodes located at the intersections between the scanning lines and data lines. The scanning lines are selected sequentially. During a period during which each scanning line is selected, a pre-charging voltage is applied to blocks into which the data lines are grouped. Thereafter, an image signal to be applied to a first data line belonging to a selected block and adjoining a succeeding block is corrected in advance based on a predicted change in the voltage on a second data line belonging to the succeeding block and adjoining the first data line. The corrected image signal is then applied to the first data line. The voltage change on the second data line is preferably predicted based on the image signal to be applied to the second data line and the pre-charging voltage.
According to another exemplary embodiment of the present invention, the data lines are pre-charged before image signals are applied to the data lines. Once the pre-charging signal is set to a proper level, the time required for application of the image signals can be minimized. Moreover, the voltage change on the second data line is derived from a change from in the pre-charging signal to an image signal. Therefore, the voltage change on the second data line can be predicted accurately based on the image signal to be applied to the second data line and the pre-charging signal.
An electro-optical device may have the sampling transistors for sequentially sampling the image signals and applying them to the data lines. In this case, the voltage change on the second data line is preferably predicted based on the image signal to be applied to the second data line, a voltage drop occurring at an associated sampling transistor, and the pre-charging signal. According to the various exemplary embodiments of the present invention, the voltage change on the second data line may be predicted in consideration of the voltage drop. Irregular luminance occurring in portions of a displayed image coincident with the borders of the blocks can be minimized more successfully.
According to another exemplary embodiment of the present invention, an image processing circuit is to be adapted to an electro-optical device having a plurality of scanning lines, a plurality of data lines, and transistors and pixel electrodes located at the intersections between the scanning lines and data lines. The scanning lines are selected sequentially. During a period during which each scanning line is selected, after a pre-charging voltage is applied to the data lines, parallel-form image signals are applied to each of blocks into which the data lines are grouped. The image processing circuit includes a parallel circuit, a correction circuit, and an output circuit. The parallel circuit expands an input image signal in terms of a time base, converts it from a serial form to a parallel form according to the number of data lines constituting each block, and thus produces a plurality of parallel-form image signals. The correction circuit corrects a parallel-form image signal, which is to be applied to a first data line belonging to a certain block and adjoining a succeeding block, according to a predicted change in the voltage on a second data line belonging to the succeeding block and adjoining the first data line. The output circuit outputs the corrected parallel-form image signal together with the other parallel-form image signals.
According to another exemplary embodiment of the present invention, an input image signal is expanded in terms of a time base, and converted from a serial form to a parallel form. A plurality of parallel-form image signals is thus produced. A parallel-form image signal to be applied to a first data line belonging to a certain block and adjoining a succeeding block is specified from among the plurality of parallel-form image signals. A change in the voltage on a second data line belonging to the succeeding block is predicted. The image signal to be applied to the first data line is corrected in advance based on the predicted potential change, and applied to the first data line. Even if noise stemming from the voltage change on the second data line enters the first data line through a coupling capacitor, the noise is canceled by the corrected image signal. Consequently, irregular luminance occurring in portions of a displayed image coincident with the borders among the blocks can be minimized successfully.
According to another exemplary embodiment of the present invention, in the electro-optical device, during the period during which each scanning line is selected, after a predetermined pre-charging voltage is applied to the data lines, the parallel-form image signals may be applied to each of the blocks into which the data lines are grouped. In this case, the correction circuit preferably predicts the voltage change on the second data line according to the parallel-form image signal to be applied to the second data line and the pre-charging voltage. The voltage change can thus be predicted accurately. The correction can be achieved precisely. Consequently, irregular luminance occurring in portions of a displayed image coincident with the borders among the blocks can be minimized more successfully.
According to another exemplary embodiment of the present invention, the electro-optical device may have the scanning lines, data lines, transistors, and pixel electrodes formed on one substrate, and have opposite electrodes formed on the other substrate opposed to the substrate. During the period during which each scanning line is selected, after the pre-determined pre-charging voltage is applied to the data lines, the parallel-form image signals may be applied to each of the blocks, into which the data lines are grouped, via sampling transistors. In this case, the output circuit preferably combines the corrected parallel-form image signal with the other parallel-form image signals, reverses the polarity of the image signals with the potential at the opposite electrodes as a reference according to a polarity reversing signal of a certain cycle, and outputs the resultant image signals. Moreover, the correction circuit preferably predicts the voltage change on the second data line according to the parallel-form image signal to be applied to the second data line, the pre-charging voltage, and a voltage drop occurring at an associated sampling transistor.
When a liquid crystal is adopted as an electro-optical material, an alternating voltage must be applied to the liquid crystal in order to prevent deterioration of the liquid crystal. In this case, the output circuit reverses the polarity of the parallel-form image signals with the potential at the opposite electrodes as a reference according to the polarity reversing signal, and then outputs the resultant image signals. Although each image signal exhibits the one and only voltage level associated with a certain gray-scale level irrespective of its polarity, the voltage drop at an associated sampling transistor is different between the polarities of the image signal. According to the various exemplary embodiments of the present invention, the potential change on the second data line is predicted accurately based on the parallel-form image signal, pre-charging voltage, and voltage drop. Irregular luminance occurring in portions of a displayed image coincident with the borders among the blocks can be minimized more successfully.
In the electro-optical device, during the period during which each scanning line is selected, after the predetermined pre-charging voltage is applied to the data lines, the parallel-form image signals may be applied to each of the blocks into which the data lines are grouped. Moreover, the input image signal may be an analog signal. In this case, the correction circuit preferably includes a sample-and-hold circuit, a correcting signal production circuit, and a synthesizer circuit. The sample-and-hold circuit samples and holds the input image signal for each block, and outputs a parallel-form image signal to be applied to the second data line. The correcting signal production circuit produces a correcting signal according to the parallel-form image signal output from the sample-and-hold circuit and the pre-charging voltage. The synthesizer circuit synthesizes a parallel-form image signal, which is output from the parallel circuit and is to be corrected, with the correcting signal, and outputs a corrected parallel-form image signal.
In this case, the sample-and-hold circuit specifies a parallel-form image signal to be applied to the second data line, that is, a signal to be applied to a data line that causes noise. The correcting signal production circuit produces a correcting signal according to the parallel-form image signal and pre-charging voltage. The noise entering the first data line stems from a change in the voltage on the second data line. The voltage change on the second data line is derived from a change from the pre-charging voltage to the parallel-form image signal. The correcting signal therefore reflects an accurately predicted change in the voltage on the second data line. Even if noise stemming from the voltage change on the second data line enters the first data line via a coupling capacitor, the noise is canceled by the corrected parallel-form image signal. Consequently, irregular luminance occurring in portions of a displayed image coincident with the borders among the blocks can be minimized successfully.
According to another exemplary embodiment of the present invention, the input image signal may be an analog signal. In this case, the correction circuit preferably includes a sample-and-hold circuit, a first calculation circuit, a second calculation circuit, a correcting signal production circuit, and a synthesizer circuit. The sample-and-hold circuit samples and holds the input image signal for each block, and outputs a parallel-form image signal to be applied to the second data line. The first calculation circuit calculates the voltage drop according to the parallel-form image signal output from the sample-and-hold circuit and the polarity reversing signal. The second calculation circuit calculates a writing voltage to be applied to the second data line according to the voltage drop calculated by the first calculation circuit and the parallel-form image signal output from the sample-and-hold circuit. The correcting signal production circuit produces a correcting signal according to the writing voltage and pre-charging voltage. The synthesizer circuit synthesizes the parallel-form image signal, which is output from the parallel circuit and is to be corrected, with the correcting signal, and outputs a corrected parallel-form image signal.
According to another exemplary embodiment of the present invention, the correcting signal can be produced in consideration of the voltage drop occurring at an associated sampling transistor. Irregular luminance occurring in portions of a displayed image coincident with the borders among the blocks can be minimized more successfully.
An image processing circuit in accordance with another exemplary embodiment of the present invention is to be adapted to an electro-optical device having a plurality of scanning lines, a plurality of data lines, and transistors and pixel electrodes located at the intersections between the scanning lines and data lines. The scanning lines are selected sequentially. During a period during which each scanning line is selected, parallel-form image signals are applied to each of blocks into which the data lines are grouped. The image processing circuit includes a correction circuit and a parallel processor. The correction circuit specifies an image signal, which is to be applied to a first data line belonging to a certain block and adjoining a succeeding block, by sampling an input image signal. The correction circuit then corrects the image signal according to a predicted change in the voltage on a second data line belonging to the succeeding block and adjoining the first data line. The parallel processor expands an output signal of the correction circuit in terms of a time base, converts it from a serial form to a parallel form according to the number of data lines constituting each block, and thus produces a plurality of parallel-form image signals.
According to another exemplary embodiment of the present invention, an image signal to be applied to the first data line belonging to a certain block and adjoining a succeeding block is specified by sampling the input image signal. A change in the voltage on the second data line belonging to the succeeding block is predicted. The image signal to be applied to the first data line is corrected in advance based on the predicted voltage change, and then applied to the first data line. Even if noise stemming from the potential change on the second data line enters the first data line via a coupling capacitor, the noise is canceled by the corrected image signal. Consequently, irregular luminance occurring in portions of a display image coincident with the borders among the blocks can be minimized successfully.
According to another exemplary embodiment of the present invention, the input image signal may be a digital signal. In this case, the correction circuit preferably includes a selection circuit, a memory circuit, and a synthesizer circuit. The selection circuit selects the input image signal for each block during one specified sampling period. In the memory circuit, signal voltage levels are stored in association with correction voltage levels. A correcting signal whose voltage level is associated with that of an output signal of the selection circuit is output from the memory circuit. The synthesizer circuit synthesizes the input image signal with the correcting signal.
In the electro-optical device, during the period during which each scanning line is selected, after the predetermined pre-charging voltage is applied to the data lines, the parallel-form image signals may be applied to each of blocks into which the data lines are grouped. In this case, the correction voltage levels are preferably determined based on the pre-charging voltage and the signal voltage levels. Consequently, the potential change on the second data line is predicted based on the pre-charging voltage and signal voltage level, and therefore predicted accurately.
Preferably, the memory circuit has a correction table listing voltage levels to be applied to the second data line and represented by image data. Consequently, irregular luminance occurring in portions of a displayed image coincident with the borders among the blocks can be minimized successfully.
The image processing circuit in accordance with another exemplary embodiment of the present invention is to be adapted to an electro-optical device having the scanning lines, data lines, transistors, and pixel electrodes formed on one substrate, and having opposite electrodes formed on the other substrate opposed to the substrate. During a period during which each scanning line is selected, after the predetermined pre-charging voltage is applied to the data lines, the parallel-form image signals are applied to each of the blocks, into which the data lines are grouped, via sampling transistors. The image processing circuit includes a polarity reversal circuit for reversing the polarity of the plurality of parallel-form image signals output from the parallel processor with the potential at the opposite electrodes as a reference according to a polarity reversing signal of a certain cycle. The input image signal is a digital signal representing input image data. The correction circuit includes a selection circuit, a first memory circuit, a second memory circuit, a reader circuit, and a synthesizer circuit. The selection circuit selects the input image data for each block during one specified sampling period. Voltage levels to be represented by image data are stored in association with voltage levels to be represented by correction data, which is used to correct an input image signal of positive polarity, in the first memory circuit. Voltage levels to be represented by image data are stored in association with voltage levels to be represented by correction data, which is used to correct an input image signal of negative polarity, in the second memory circuit. The reader circuit places output data of the selection circuit in the first memory circuit or second memory circuit according to the polarity reversing signal, and reads associated correction data. The synthesizer circuit synthesizes the input image data with the correction data read by the reader means.
According to another exemplary embodiment of the present invention, the correction data for an input image signal of positive polarity and the correction data for an input image signal of negative polarity are stored in the first memory circuit and second memory circuit respectively. Correction data can therefore be produced according to a polarity represented by the polarity reversing signal. Namely, a correcting signal can be produced in consideration of the voltage drop occurring at an associated sampling transistor. Irregular luminance occurring in portions of a display image coincident with the borders among the blocks can be minimized more successfully.
The input image signal may be a digital signal. Accordingly, the parallel processor may include a D/A converter and a parallel circuit. The D/A converter converts the digital output signal of the correction circuit into an analog form. The parallel circuit expands the analog signal output from the D/A converter in terms of a time base, converts it from a serial form to a parallel form according to the number of data lines constituting each block, and thus produces a plurality of analog parallel-form image signals. In this case, the D/A converter may handle a signal of one channel. The analog signal is converted from the serial form to the parallel form.
The input image signal may be a digital signal. Accordingly, the parallel processor may include a parallel circuit and a D/A converter. The parallel circuit expands a digital output signal of the correcting circuit in terms of a time base, converts it from a serial form to a parallel form according to the number of data lines constituting each block, and thus produces a plurality of digital parallel-form image signals. The D/A converter converts the plurality of digital parallel-form image signals produced by the parallel circuit into an analog form, and outputs a plurality of analog parallel-form image signals. In this case, the digital signal is converted from the serial form to the parallel form. Consequently, digital parallel-form image signals exhibiting the same characteristics can be produced.
An electro-optical device in accordance with another exemplary embodiment of the present invention consists mainly of the foregoing image processing circuit, a scanning line drive circuit, a block drive circuit, and a pre-charge circuit. The scanning line drive circuit selects the scanning lines sequentially. The block drive circuit sequentially selects blocks, into which the data lines are grouped, during a period during which each scanning line is selected, and applies parallel-form image signals to the data lines belonging to a selected block. Before a block is selected, the pre-charge circuit applies a pre-charging voltage to the data lines belonging to the block. Preferably, the pre-charge circuit sets the pre-charging voltage to a voltage level associated with a substantially black level of a gray scale or a substantially white level thereof. Consequently, the pre-charging voltage whose level is associated with the substantially black level is applied to the data lines in a normally-white mode, while the pre-charging voltage whose level is associated with the substantially white level is applied thereto in a normally-black mode. This results in distinct contrast.
Electronic equipment in accordance with another exemplary embodiment of the present invention is characterized in that an electro-optical device is adopted as a display unit. The electronic equipment is, for example, a video projector, a note-shaped personal computer, or a portable telephone.